Astera Labs
Latest active Astera Labs jobs
Astera Labs
Product
ALAB
Stock symbolNASDAQ
Stock exchange201-500
Employees2017
FoundedAstera Labs is a fabless semiconductor company focused on connectivity solutions for data-centric systems, delivering robust PCIe connectivity and overcoming performance bottlenecks.
Astera Labs jobs
Hardware Engineer
Embedded Developer
Physical Design Engineer
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Astera Labs
Latest active Astera Labs jobs
Hardware Engineer
Embedded Developer
Physical Design Engineer
ASIC Engineer
Product Manager
System Engineer
Senior Electrical Validation Engineer-PCIe/Ethernet
Santa Clara
2+ years in supporting or developing complex SOC/Silicon products for server, storage, and/or networking applications.Experience in debug and bring-up of complicated SOC’s with high-speed interfaces such as PCIe/802.3 Ethernet.Experience in system testing, characterization, margin analysis, and optimization of high-speed, multi-gigabit data links over long and short channels.Experience in PCIe or Ethernet especially electrical compliance sections.Experience in signal integrity, especially as it relates to PCIe/Ethernet testing and CEM/NVMe interfaces.Experience in schematic capture and PCB layout tools from Cadence, Altium, etc.Experience in simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues.
Senior Field Applications Engineer
Santa Clara
Minimum of 5 years’ experience working with cloud service providers and server OEM customers to design in complex SOC/Silicon products for server & storage.Experience with high-speed protocols like 25G, 50G, 100G Ethernet etc.Experience with QSFP, QSFP-DD, and OSFP pluggable modules development/support.Silicon/System bring-up and debug experience in customer systems.Experience working with contract manufactures to support NPI and volume production.Experience with high-speed signal integrity issues.Experience with lab equipment including protocol analyzers and oscilloscopes.Experience with Python scripting or other equivalent programming languages.Development/support for Ethernet switch products.Understanding and capturing performance metrics like latency, bandwidth, power for CPU, memory, PCIe, DDR.Knowledge of simulation, schematic capture, and PCB layout tools from Cadence, Altium and others etc.Development/support for Ethernet, PCIe, CXL, DDR4/DDR5 in data center systems.Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug
Hardware Optical Board Design Engineer
Santa Clara
5 years in system-level board design, from component selection and schematic capture through board bring-up, debug, optimization, and validation.Experience in high-speed board design techniques and methodologies, preferably in the enterprise and data center system space, such as PCIe add-in cards, servers, JBOGs/JBODs, networking switches/routers/interconnects, optics, active electrical cables, etc.Experience in schematic capture and PCB layout tools from Cadence, Altium, and others.Experience in Allegro layout tool (for reviewing designs).Experience in power architecture in both circuit (DC/DC POL converters) and distribution (power integrity).Experience in signal and power integrity challenges and solutions.Experience in designing systems with high-speed NRZ/PAM4 SERDES-based protocols such as PCIe (3.0 and above), Ethernet (25G and above), etc., and/or memory interfaces such as (LP)DDR4/5.Experience in board bring-up and validation.Experience in silicon/PCB bring-up and debug.Experience in taking products from concept to mass production.Experience working with contract manufacturers, PCB vendors, and other external suppliers.Experience working with mechanical and thermal teams to create achievable system design specifications.Experience in hardware design around FPGAs and MCUs, including pin mapping and evaluating different SKUs against a list of hardware requirements.Experience designing PCIe/CEM cards, paddle cards/active copper cable applications.Experience designing complete high-speed channels may include IC sockets, connectors, and cables.Experience working with silicon characterization/validation teams to ensure device performance is readily achievable in customer systems.Experience working with off-shore CMS.Experience in technical writing skills to generate clear, precise documentation such as hardware specifications and user guides for internal and customer-facing audiences.Experience in adjacent areas such as manufacturing, quality, and compliance.
Hardware Electrical Validation Engineer
Santa Clara
3 years in test or design.Experience in complex electronics products.Experience with lab equipment (scopes, vna, tdr, e-loads, environmental chambers).Experience with scripting automation tasks with lab equipment.Experience with measurements of high speed interfaces (PCIE, DDR, 25/50g/100g SERDES).Experience with EMI/EMC compliance.Experience with ASIC/Silicon development process.Experience working with CMS (off-shore a plus).
PCBA / Product Engineer / NPI
Santa Clara County
5+ years in NPI/EPE roles.5+ years in test engineering or electronics manufacturing.Experience in high-tech manufacturing processes, NPI activities, and product development lifecycle.Experience working with off-shore contract manufacturers.Experience in DFM, Design for Testability (DFT), and Design for Assembly (DFA) methodologies.Experience with Bill of Material (BOM) structuring and risk management with PLM tools (e.g., Arena, Agile).Experience in root cause analysis of contract manufacturing issues.Experience implementing process documentation and manufacturing best practices.
Hardware Lab Engineer
Santa Clara
5 years in rework and assembly of complex PCBA prototypes.Experience in high-speed measurements.Experience in configuring and setting up computers and test equipment.
Senior Field Applications Engineer
Austin
5 years in designing complex SOC/Silicon products for server & storage.Experience in high-speed & low-speed protocols like PCIe, Ethernet, CXL, DDR, NVMe, I2C, SPI, UART.Experience in PCIe LTSSM at a physical layer level, associated standards, and debug.Experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred.Silicon/system bring-up and debug experience in customer systems.Experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTS.Experience in high-speed board design techniques, and understanding of data center systems like server and PCIe add-in cards.
Senior Package Design Engineer
Santa Clara
5 years in CADENCE APD/SIP.Experience in large FCBGA/FCCSP package design in high-speed SOC.Experience in BGA package substrate technologies and assembly process.Experience in package reliability, SI/PI.Experience in package manufacturing flow, supply chain, reliability, risk management and failure analysis.Experience in multi-chip, interposer, 2.5D or heterogeneous package design.Experience in scripting languages for design and reporting automation.
Senior Package Design Engineer
San Francisco Bay Area
5 years in Cadence APD/SIP.Experience in large FCBGA/FCCSP package design in high-speed SoC.Experience in BGA package substrate technologies and assembly process.Experience in package reliability, SI/PI.Experience in package manufacturing flow, supply chain, reliability, risk management, and failure analysis.
Older Listing
Tech Lead Firmware Engineer (DDR technologies)
Santa Clara
5+ years in developing firmware using C in embedded environments.Experience in DDR technology internals (DDR training, DDR RAS, PMIC, RCD etc.).Experience in debugging DDR related issues.Experience in post-silicon bring up and validation of DDR memory interfaces.Experience in pre-silicon DDR bring up.Experience in working with cross-functional teams and partners.Experience with RDIMMs, DDR controller/phy tuning.Experience in server memory performance and stability tuning for latency and bandwidth.
Older Listing
Senior Principal System Validation Engineer
Santa Clara
≥12 years' experience supporting or developing complex SOC/Silicon products for server, storage, and/or networking applications.Experience with silicon/system bring-up, validation, and debug experience, including in customer systems.Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.
Older Listing
Sr. Principal Product Manager
Santa Clara
Office
10+ years in product management, product marketing, applications or other customer-facing product roles within the semiconductor industry
Older Listing
Principal Diagnostic Platform Software Engineer
Santa Clara
8+ years in diag, hardware bring-up, test or manufacturing automationExperience in modern software developmentProficiency in PythonExperience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturingSystem debug experienceEmbedded programming and good knowledge of OS internals (Linux/Unix)Knowledge of common inter connecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, switch chips, SSL offload, TCAM programmingExperience with DDR5
Older Listing
Principal ASIC Engineering Program Manager
Santa Clara
5 or more years of relevant ASIC product experience in an electronics product or semiconductor company.5 or more years of experience as an ASIC program manager.
Older Listing
Senior Electrical Engineer
Santa Clara
5+ years in system-level board design.Experience in high-speed board design techniques.Experience in schematic capture and PCB layout tools.Experience in power architecture.Experience in signal and power integrity challenges.Experience in designing systems with high-speed NRZ/PAM4 serdes-based protocols.Experience in board bring-up and validation.Experience in silicon/PCB bring-up and debug.Experience in taking products from concept to mass production.Experience in working with contract manufacturers, PCB vendors, and other external suppliers.
Older Listing
Principal PCIe/Ethernet Electrical Validation Engineer
Santa Clara
8+ years in supporting or developing complex SoC/silicon products.Experience in leading SoC debug and development for high-speed interfaces.Experience in system testing, characterization, margin analysis and optimization of high-speed PCIe/CXL data links.Strong Python scripting ability.Proficiency using high-speed lab equipment.
Older Listing
Signal/Power Integrity Engineer
Santa Clara
5+ years in supporting or developing complex SoC/silicon products.10+ years in high-speed SI/PI design, simulation, and measurement.Experience in 2D and 3D simulation with CADENCE/Mentor/Ansys/ADS/etc. toolsets.Experience in EM modeling of connector structures.Experience in high-speed SerDes measurement, channel simulation, and equalization.Experience in DDR4/5 memory bus designs.Experience in multi-level and NRZ signaling, COM, BER, jitter analysis.Experience in system testing, characterization, margin analysis, and optimization of high-speed PCIe/CXL data links.Experience in DDR 4/5 post-silicon electrical validation.
Older Listing
Sr. Hardware Optical Engineer
Santa Clara
5 years in system-level board design.Experience in high-speed board design techniques.Experience with PCB layout tools like Cadence and Altium.Experience in board bring-up and validation.Experience designing PCIe add-in cards.